IEC 61280-2-1 pdf download

IEC 61280-2-1 pdf download

IEC 61280-2-1 pdf download Fibre optic communication subsystem test procedures – Part 2-1: Digital systems – Receiver sensitivity and overload measurement
1 Scope and object
This part of IEC 61 280 describes the test procedures applicable to digital fibre optic communication and data systems.
The object of this test procedure is to measure the minimum and maximum optical powers required and allowed at the optical input port of a fibre optic system to ensure its operation within specified limits. Another objective is to verify that the guaranteed error performance is obtained at the minimum and the maximum optical input powers specified by the terminal equipment manufacturer.
Figure 1 shows the typical elements associated with optical fibre systems. Optical amplifiers or regenerators may be used in long haul telecom systems, but are not usually associated with data transport systems such as Ethernet, etc. In bi-directional systems the transmitter and corresponding receiver are usually co-located, as indicated by the dotted lines. This specification is concerned with the characteristics of the optical input interface of the receiver, amplifier or regenerator shown.
It should be noted that the performance of fibre optic receivers may differ for different signal formats. It is therefore necessary to use the signal format that represents actual operating conditions.
2 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
bit error ratio ( BER)
the number of errored bits divided by the total number of bits, over some stipulated period of time [IEC 61 931 , definition 2.9.33]
bit sequence
a defined sequence of ones (1) and zeros (0) in a digital signal
bit pattern
a predetermined sequence of 1 ’s and 0’s in a digital signal which is repeated at regular intervals
errored block ratio ( EBR)
the number of errored blocks, containing a defined number of digits, divided by the total number of blocks received in a specified period of time. An errored block may contain more than one errored bit
overload level
the maximum input power above which a specified quality of performance is no longer achieved
3 3.1 Apparatus General
The test setup is shown in Figure 2. It is important that test cords 3 and 4 are of a similar type and make and are of equal length.
3.2 BER test set
The BER test set is made up of the elements described here.
3.2.1 Data generator The data generator of the BER test set shall be capable of providing a data input to the system which may be a pseudo-random sequence or otherwise specified bit pattern with the signal format (pulse shape, amplitude, etc.) that is consistent with the requirements at the system input interface of the EUT.

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