IEC 62416 pdf download

IEC 62416 pdf download Semiconductor devices – Hot carrier test on MOS transistors
1 Scope
This standard describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.
2 Abbreviations and letter symbols
In this document the following abbreviations and letter symbols apply:
MOS Metal Oxide Semiconductor
NMOS n-channel MOS transistor
PMOS p-channel MOS transistor
(C)MOS Complementary MOS
L [μm] length of polysilicon gate of MOS transistor
W [μm] width of polysilicon gate of MOS transistor
L nominal [μm] minimum L allowed by the design rules of the process
W nominal [μm] minimum W allowed by the design rules of the process
V gs [V] gate-source voltage of MOS transistor
V ds [V] drain-source voltage of MOS transistor
V bs [V] backgate-source voltage of MOS transistor
I ds [μA]: drain-source current of MOS transistor
I b [μA] substrate current of MOS transistor
I g [nA] gate current of MOS transistor
V gs,stress [V] V gs biasing condition during hot carrier stress
V ds,stress [V] V ds biasing condition during hot carrier stress
V ds,use_max [V] maximum V ds allowed by the design rules of the process as stated in the design manual
V ds,breakdown [V] V ds at which avalanche or punch-through currents become dominant;
defined as V ds at which I ds = 1 ,5 × (I ds at V ds,use_max ) while V gs = V ds,use_max V t [V] threshold voltage of MOS transistor defined as V gs voltage at which I ds = 0,01 × W / L [μA]. Other (commonly agreed) definitions of V t are also allowed as long as this is clearly reported.
g m [μA/V] transconductance of MOS transistor
g m,max [μA/V] maximum transconductance of MOS transistor
I ds,sat [μA] saturated drain-source current at V gs = V ds = V ds,use_,max ; I ds,sat_forward measured with source and drain having same polarity as during stress,I ds,sat_reverse measured with source and drain polarity interchanged with respect to stress.
L( MOST) length of the square MOS transistor (L = W)
g m,max ( MOST) g m,max of the square MOS transistor (L = W)
3 Test structures
For the evaluation of the hot carrier degradation vulnerability of a technology, nominal transistors (L = L nominal ) are recommended. The following gate lengths are recommended when lifetime extrapolation versus L is needed (see 9.1 ): L = 1 ,0 × L nominal , L = 1 ,5 × L nominal , L = 2,0 × L nominal , L = 5,0 × L nominal , L = W.